The present disclosure relates to semiconductor devices and methods for fabricating the semiconductor devices, and particularly relates to semiconductor devices which include a metal-insulator-semiconductor field-effect transistor (MISFET) having a source/drain region including a silicon compound layer, and methods for fabricating the semiconductor devices.
A distortion technique of enhancing the drive capability of a MISFET (hereinafter referred to as a “MIS transistor”) by applying a stress to the channel region of the MIS transistor has been employed to improve the performance of a semiconductor integrated circuit device. In the case of p-type MIS transistors, it is known that if a compressive stress is applied to the channel region in the gate length direction, the mobility of carriers is increased, and the drive capability of the p-type MIS transistor is enhanced. Examples of methods for applying a compressive stress to the channel region in the gate length direction includes forming, in a source/drain region, a SiGe layer having a larger lattice constant than the lattice constant of a silicon substrate (see, e.g., Patent Document 1: U.S. Pat. No. 6,621,131 (U.S. Patent Publication No. 2003/0080361); Non-Patent Document 1: T. Ghani et al., “A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors,” IEDM Tech. Digest, pp. 978-980, 2003; and Non-Patent Document 2: Z. Luo et al., “Design of High Performance PFETs with Strained Si Channel and Laser Anneal,” IEDM Tech. Digest, pp. 495-498, 2005).
A semiconductor device in which a p-type MIS transistor having a SiGe layer formed in a source/drain region, and an n-type MIS transistor are formed on the same semiconductor substrate will be described below, with reference to FIGS. 8A-8C, FIGS. 9A-9C, and FIGS. 10A-10C. FIG. 8A to FIG. 10C are cross-sectional views of a conventional semiconductor device in the gate length direction which sequentially show steps of fabricating the conventional semiconductor device. In FIG. 8A to FIG. 10C, the term “pMIS region” shown on the left side is a region where the p-type MIS transistor is formed, and the term “nMIS region” shown on the right side is a region where the n-type MIS transistor is formed.
Initially, as shown in FIG. 8A, an isolation region 101 is selectively formed in an upper portion of a semiconductor substrate 100. As a result, a first active region 100a surrounded by the isolation region 101 is formed in the pMIS region of the semiconductor substrate 100. A second active region 100b surrounded by the isolation region 101 is also formed in the nMIS region of the semiconductor substrate 100. After that, an n-type well region 102a is formed in the pMIS region of the semiconductor substrate 100, and a p-type well region 102b is formed in the nMIS region of the semiconductor substrate 100.
Next, first and second gate electrode formation portions 105A, 105B which respectively include first and second gate insulating films 103a, 103b, first and second gate electrodes 104a, 104b, and first and second protective insulating films 105a, 105b, are formed on the first and second active regions 100a, 100b. 
Next, first and second offset spacers 106a, 106b are formed on side surfaces of the first and second gate electrode formation portions 105A, 105B. Then, p-type extension implantation regions 107a are formed in the first active region 100a on lateral sides of the first gate electrode formation portion 105A. Also, n-type extension implantation regions 107b are formed in the second active region 100b on lateral sides of the second gate electrode formation portion 105B.
Next, as shown in FIG. 8B, first and second sidewalls 109A, 109B which respectively include first and second inner sidewalls 108a, 108b, and first and second outer sidewalls 109a, 109b, are formed on the side surfaces of the first and second gate electrode formation portions 105A, 105B, with the first and second offset spacers 106a, 106b interposed between the first and second gate electrode formation portions 105A, 105B and the first and second sidewalls 109A, 109B.
Next, as shown in FIG. 8C, a protective insulating film 110 which covers the second gate electrode formation portion 105B, the second offset spacer 106b, the second sidewall 109B, and the n-type extension implantation region 107b is formed on the second active region 100b. 
Next, the first active region 100a is etched using the first sidewall 109A and the protective insulating film 110 as a mask. As a result, trenches 111 are formed in the first active region 100a on lateral sides of the first sidewall 109A.
Next, as shown in FIG. 9A, a SiGe layer 112 doped with a p-type impurity is formed in each of the trenches 111. Since the SiGe layer 112 is doped with the p-type impurity, the region of the SiGe layer 112 is a p-type impurity-introduced region.
Next, as shown in FIG. 9B, the protective insulating film 110 and the first and second protective insulating films 105a, 105b are removed.
Next, as shown in FIG. 9C, n-type source/drain injection regions 113 are formed in the second active region 100b on lateral sides of the second sidewall 109B.
Next, as shown in FIG. 10A, the p-type and n-type impurities contained in the p-type and n-type extension implantation regions 107a, 107b are activated by a thermal treatment to form p-type and n-type extension regions 114a, 114b. The p-type impurity contained in the region of the SiGe layer 112 (i.e., the p-type impurity-introduced region) is activated to form a p-type source/drain region 115a. The n-type impurity contained in the n-type source/drain injection region 113 is activated to form an n-type source/drain region 115b. 
Next, as shown in FIG. 10B, first and third silicide layers 116a, 116b are formed on the first and second gate electrodes 104a, 104b, and second and fourth silicide layers 117a, 117b are formed on the p-type and n-type source/drain regions 115a, 115b. 
Next, as shown in FIG. 10C, a stress insulating film 118 which causes a tensile stress in the gate length direction of the channel region in the second active region 100b is formed on the entire surface of the semiconductor substrate 100.
Conventional semiconductor devices are formed in this manner.